1. Field of the Invention
This invention relates in general to an associative memory and, more particularly, to an associative memory having a simplified memory cell circuitry.
2. Description of the Background Art
FIG. 8 shows a circuit diagram showing an example of a memory cell circuit in a conventional associative memory. This memory circuit may be seen for example in a Digest of Technical Papers, pp. 42 to 43, made public in the IEEE International Solid State Circuit Conference held in 1985. Referring to FIG. 8, this memory cell includes a SRAM section constituted by PMOS transistors 13, 14 and NMOS transistors 5 to 8 and adapted for holding data signals, and a coincidence detecting section constituted by NMOS transistors 9 to 12. The SRAM section is connected to a word line WL and bit lines BL, BL. The coincidence detecting section is connected to a match line ML and bit lines BL, BL.
When a data signal "1" is to be written during writing in this memory cell, the word line WL and the bit line BL are brought to a level of the source voltage Vcc, referred to hereinafter as the high level, while the bit line BL is brought to a level of ground voltage, referred to hereinafter as a low level. Hence, transistors 6 and 14 are turned on, while transistors 7 and 13 are turned off. After the word line WL is brought to the low level, transistors 5 and 8 are turned off, so that the data signal "1" is held in the SRAM section. On the other hand, when a data signal "0" is to be written in this memory cell, the word line WL and the bit line BL are brought to the high level, while the bit line BL is brought to the low level.
When the data signal "1" stored in a memory cell is read out during read out operation, the bit lines BL, BL are precharged to a voltage Vcc/2. The word line WL is then brought to the high level. Since the data signal "1" is stored in the SRAM section, the nodes B1 and B2 are brought to the low level and the high level, respectively. Thus, after the transistors 5 and 8 are turned on responsive to the high level voltage on the word line WL, the voltages on the bit line BL is increased, while the voltage at the bit line BL is decreased. These changes in voltages are amplified by a sense amplifier, not shown, for reading out the signal "1". The read out operation of the data signal "0" is performed in the similar manner.
The coincidence detecting operation is hereinafter explained. In the following explanation, it is assumed that a data signal "1" is stored in the memory cell. First, the coincidence detection line ML is precharged to the source voltage Vcc. The word line WL is brought to the ground voltage. Since the signal "1" is held in the SRAM section, transistor 10 is turned off, while transistor 12 is turned on. In this state, data signals for comparison are supplied to this memory cell via bit lines BL and BL. For example, when a comparison data signal "1" is supplied for comparison, the bit line BL is brought to the high level, while the bit line BL is brought to the low level. As described above, the transistors 10 and 12 are turned off and on, respectively, responsive to the data signal "1" stored in this memory cell. The transistors 9 and 11 are turned on and off, respectively, responsive to the high level voltage on the bit line BL and the low level voltage on the bit line BL, respectively. As a result, the coincidence detection line ML is not connected to ground via transistors 9 to 12.
On the other hand, when a comparison data signal "0" is supplied for comparison, the bit line BL is brought to the low level, while the bit line BL is brought to the high level. The transistor 11 is turned on responsive to the high level voltage on the bit line BL. Thus, the coincidence detection line ML is connected to ground via transistors 11 and 12, so that the coincidence detection line ML is brought to the low level.
The operation for coincidence detection when the data signal "0" is stored in the memory cell is performed in the similar manner, so that the description is omitted for simplicity.
Since the voltage on the coincidence section line ML is changed in this manner responsive to the results of comparison of data signal, the result of comparison may be detected by detecting the voltage on the match line ML.
FIG. 9 shows a circuit diagram showing another example of a memory circuit of a conventional associative memory. This example may be seen for example in a thesis entitled "20 kB CAM LSI", pp. 31 to 37, by Ogura et al in a technical report CPSY 87-33 of the Electronics Information Communication Society of 1987. Referring to FIG. 9, this memory cell include a SRAM section constituted by NMOS transistors 15 to 18 and registers 22 and 23, and a coincidence detecting section constituted by NMOS transistors 19 to 21. The SRAM section is connected to a word line WL and bit lines BL and BL. The coincidence detecting section is connected to data search lines SL and SL supplied with data search signal and to the match detection line ML.
During the operation for coincidence detection, the data search signals of opposite signs or polarities are supplied to the data search lines SL and SL. Since the data signal is held in the SRAM section, one of nodes C1 and C2 is brought to the high level. When the voltage at the node C2, for example, is at the high level, transistor 19 is turned on upon application of search data setting a high level voltage at the node C2. Thus, the coincidence detection line ML is brought to the low level voltage. Thus, in the memory cell shown in FIG. 9, the operation of coincidence detection may be performed similarly to the case of the memory cell of FIG. 8.
In the memory cells shown in FIGS. 8 and 9, ten and nine devices are used, respectively. Since the number of devices necessary for each cell in the conventional associative memory is not small, so that the circuitry is complicated. As a result, difficulties are presented in elevating the degree of integration of associative memories.
A prior art example having a particular reference to the present invention may be seen in the Japanese Patent Publication Gazette No. 96799/1988. This prior art example shows an associative memory including a complementary memory cell circuit in which the operation for coincidence detection can be performed without the necessity of using signals for commanding the operation of coincidence detection.